Alpha Data Releases ADM-PA100 Adaptive Computing Acceleration Platform
Alpha Data releases ADM-PA100, the first implemented adaptive computing acceleration platform (ACAP)-based Data Processing Unit suitable for PCIe deployment.
FREMONT, CA: Alpha Data, the pioneering supplier of Commercial Off-the-Shelf FPGA solutions, announces the release of the ADM-PA100, the first implemented adaptive computing acceleration platform (ACAP)-based Data Processing Unit suitable for PCIe implementation. It provides a fully customizable IO, available to meet customer needs in markets including Data Center, Scientific Instrumentation, Machine Learning, HPC, and Test and Measurement.
The ADM-PA100 is based around the Versal AI Core series, which includes a series of Xilinx AI Engines (dedicated VLIW processors, potent of Vector Math Processing at computing densities 5x higher than programmable logic), closely combined with Programmable Logic enabling the highly efficient deployment of custom coprocessing activities in this data flow.
The Xilinx Versal series of devices also feature an on-chip Programmable NoC, designed for hardened IP for Multi-Rate 100G Ethernet, hardened PCIe Gen4 endpoints with DMA outside the Programmable Logic, toughened DDR4 memory controllers, developed in ARM A72 and R5F CPUs, and programmable logic and DSP performance a creation on from UltraScale+ devices. The hardware adaptability and architecture of Versal AI Core ACAPs are a vital advantage over conventional accelerators that focus on a subset of applications. This allows the creation of multiple Domain Specific Architectures targeted to specific workloads.
Xilinx is delighted that Alpha Data has chosen the Versal AI Core series for its ADM-PA100 board to scale a breadth of workloads in networking, cloud, and edge markets.
The ADM-PA100 allows this programmable power available on a platform that can be implemented in PCIe as a co-processor in an x86 CPU server system or using the ARM A72 for all the general-purpose processing needs. IO flexibility is one vital advantage of ACAP and FPGA over other classes of devices, enabling data to be processed with minimal latency and maximum bandwidth. The ADM-PA100 helps this IO flexibility with a front-facing FMC+ socket supporting 24 Gigabit transceiver lanes and a complete FMC HPC interface with 160 GPIO, which can interface with a wide range of FMC IO adapters.
The ADM-PA100 comes with help for Xilinx Vivado and Viti's toolchains to allow customers maximum flexibility in developing their deployable solutions.
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