Arteris Announces the Availability of Arteris FlexNoC Physical interconnect IP

By CIOReview | Thursday, April 23, 2015
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SANTA CLARA, CA: Arteris, the inventor and supplier of silicon-proven commercial network-on-chip (NoC) interconnect IP solutions, announces the availability of Arteris FlexNoC Physical interconnect IP, a breakthrough that accelerates system-on-chip (SoC) physical design.

Arteris NoC technology uses fewer wires, enables fine-grained pipeline register placement nearly anywhere in the interconnect, and allows distributed IP placement. This technology has been providing the world’s top semiconductor design teams the benefits of minimizing wire routing congestion and reducing silicon area, cost and power consumption for many years.

Also, FlexNoC Physical interconnect IP enhances layout quality-of-results (QoR) and productivity by importing user-defined and production floorplans, automatically configuring pipelines to meet timing closure constraints, and separating the FlexNoC interconnect IP instances at a physical level so they can be routed separately from the rest of the SoC.

The benefits of FlexNoC Physical IP in reduced P&R iterations, eliminates trial-and-error timing closure with automated pipeline configuration, Optimizes Quality-of-Results (QoR),  Separates the FlexNoC interconnect physical IP from the rest of the SoC.

“Using FlexNoC Physical delivers two valuable benefits: First, it allows SoC architects to visualize the physical implications of their topologies early in the design cycle, and second, it helps the RTL implementation team to automatically add pipelines for timing closure, cutting months off complex SoC development cycles” says K. Charles Janac, President and CEO of Arteris. “We are helping customers cut down place and route cycles by providing their layout teams better starting-point data.”