Cadence's Stratus Platform to be Utilized across Entire SoC Design

By CIOReview | Friday, March 6, 2015
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FREMONT, CA: Cadence, a provider of Electronic Design Automation (EDA) and semiconductor Internet Protocol (IP), comes up with its Cadence Stratus high-level synthesis platform which can be utilized across an entire design of System-on-Chip (SoC).

Earlier, designers had to select the parts of SoC design to implement the synthesis platform. Stratus platform addresses the challenge by integrating Forte Cynthesizer (TM) and Cadence C-to-Silicon Compiler into one tool to enable physically-aware and Engineering Change Orders (ECO) aware high-level synthesis and reduce implementation changes.

The new synthesis platform is sixth generation high-level synthesis core engine to deliver better usability, scalability and Quality of Results (QoR) across the application for both control-centric and datapath-centric designs that include hundreds of blocks. It consists of intellectual property library of Input/Output (I/O) interfaces and customizable floating point datatypes to enhance productivity by 10 times.

Stratus platform also allows full architectural exploration with its full Integrated Development Environment (IDE) and automation of tool flow and evaluation capability of multiple scenarios. The tool gives uniform environment from Transaction-level modeling (TLM) models through gates to improve verification by 5 times. It delivers 20 percent better Power, Performance, and Area (PPA) and QoR.