Intellitech Introduces Interoperability among NEBULA Silicon Debugger, Intellitech iJTAGServer Bridge, and the Synopsys VCS

By CIOReview | Monday, September 21, 2015

DOVER, NH: Intellitech Corporation, manufacturer of Automatic Test Equipment (ATE) for test and silicon debug of IEEE 1149.x based products has declared interoperability between its NEBULA silicon debugger, the Intellitech iJTAGServer Bridge, and the Synopsys VCS functional verification environment.

The integrated solution enables IP providers the ability to develop and validate computer-readable IEEE complaint descriptions for Silicon Instruments, the IP blocks, especially those in a SoC (System on Chip) that are accessible via IEEE 1149.1/JTAG. These enable critical on-chip configuration, monitoring and test throughout the life-cycle of a SoC (System on Chip). PVT (Process-Voltage-Temperature) monitors, SERDES analog parameters, Electronic Chip IDs, PLL control and memory BISRs (Built-In-Self-Repair) are a few examples of Silicon Instruments which are used during first silicon bring-up, production IC test or with the IC in-situ on a PCB (Printed Circuit Board).  

Intellitech's Chief Executive Officer, CJ Clark states, “…For the first time in the industry, customers of instrument IP can not only contractually specify IEEE 1149.1-2013 compliance, but also require pre-validated IEEE 1149.1-2013 documentation and code coverage metrics from their IP provider. The SoC integrator can then take this pre-validated documentation and use it directly on ATE, avoiding the costs of re-interpretation of the IP provider's test vectors and instrument intent. The time to validate instrument operation and descriptions is not post-silicon on the IC tester; that adds risk, schedule impact and ultimately cost."

Intellitech’s NEBULA is used as front end software to develop documentation for Silicon based instrument while Synopsys VCS, verification environment provides the expected responses and code coverage metrics. NEBULA is capable of reading IEEE 1149.1-2013 complaint IP models that describe the Silicon Instrument abstractly and uses 1149.1 PDL (Procedural Description Language) to perform transactions to and from the instrument in simulation as would occur in a real SoC. IEEE 1149.1-2013 PDL is used as a complement to SystemVerilog can’t achieve. Once PDL for a Silicon Instrument is validated using Synopsys VCS, the same PDL documentation can then be re-used by the SoC integrator and the ATE engineers regardless of documentation correctness or robustness of the verification. That same instrument PDL can also be re-used by the system company using the SoC to talk to the instrument for board test or field test.