Mellanox and Cadence Partner for PCI Express 4.0 Multi-Lane 16Gbps PHY IP Interoperability

By CIOReview | Thursday, March 17, 2016
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SAN JOSE, CA: Cadence Design System, Inc. collaborated with Mellanox Technology and demonstrated its multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC’s 16nm FinFET Plus (16FF+) process. Peddling towards the conception of building next-generation green data centers, customers can now deploy Cadence’s silicon-proven IP solution for instant integration and fastest market deployment. Both the giants are set to demonstrate PCIe 4.0 architecture and its electrical interoperability between their respective PHY solutions at the 2016 TSMC Symposium on March 15, 2016 in Santa Clara, California.

“PCIe 4.0 technology throughput will enable data center applications to analyze more data and to find insights in real time. The successful interoperability with Cadence shows the increase in the PCIe 4.0 ecosystem of hardware solutions, and marks an important milestone toward building InfiniBand or Ethernet connected data centers based on the PCIe 4.0 specification.” said Gilad Shainer, Vice President of Marketing at Mellanox Technologies.

The PCI Express (PCIe®) 4.0 architecture by Cadence and Mellanox, attained the speed of 16Gbps while running 4 lanes concurrently. With such high speed data transfer, PCI Express proves to be a distinctive configuration for next-generation servers, storage and networking equipment. As a result of the collaboration, Mellanox and Cadence developed a PHY that exceeds PCIe 4.0 architecture requirements in terms of insertion loss with bit-error rate (BER) below 10-15. Cadence, one of the leading integrated circuits and electronics solution providers, also presents silicon-proven ‘Algorithmic Modeling Interface (AMI)’ models with the company’s Sigrity™ technology. The AMI models of Cadence are used to produce chip, package and board designs that deliver robust signal integrity to handle impairments such as crosstalk and insertion loss deviation.

“As an active PCI-SIG member, Cadence continues to innovate and develop IP that supports the latest PCIe specifications,” said Hugh Durdan, Vice President of Marketing for Design IP at Cadence. “Our collaboration and successful interoperability demonstration with Mellanox gives our customers peace of mind in knowing that they can incorporate Cadence IP for PCIe 4.0 technology into their designs successfully and with less risk.”