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SAN JOSE, CA: Cadence Design System, Inc. collaborated with Mellanox Technology and demonstrated its multi-lane interoperability between Mellanox’s physical interface (PHY) IP for PCIe 4.0 technology and Cadence’s 16Gbps multi-link and multi-protocol PHY IP implemented in TSMC’s 16nm FinFET Plus (16FF+) process. Peddling towards the conception of building next-generation green data centers, customers can now deploy Cadence’s silicon-proven IP solution for instant integration and fastest market deployment. Both the giants are set to demonstrate PCIe 4.0 architecture and its electrical interoperability between their respective PHY solutions at the 2016 TSMC Symposium on March 15, 2016 in Santa Clara, California.