Silicon Labs Reforms Lowest Clock Jitter with 'Clock Tree on a Chip'
FREMONT, CA: Building on a solid foundation of Internet infrastructure to meet the demands for high-speed networking, communications and data center equipment, Silicon Labs the semiconductor based company, launches lowest Jitter network synchronizer clock.
The high performance, cost effective packet network synchronizer ‘Si5348 clock IC’ enables hardware designers to implement a “clock-tree-on-a-chip” solution for Synchronous Ethernet (SyncE), IEEE 1588v2 and general purpose frequency translation for wireless and telecom infrastructure, broadband networks and data center applications.
“Networks are transitioning from circuit-switched to packet-switched systems to increase efficiency, flexibility and cost effectiveness, and as SyncE and IEEE 1588 become more widely adopted, equipment makers are looking for solutions that minimize the cost and complexity of adding packet network synchronization to a design,” says James Wilson, Marketing Director, Silicon Labs.
High-stability oscillators always play a vital role in defining the network’s overall performance in terms of frequency, time and phase accuracy. Network topologies determine the type of temperature-controlled crystal oscillator (TCXO) or oven-controlled crystal oscillator (OCXO) required at each node in the network. The Si5348 clock enables the device to be paired with any frequency TCXO/OCXO by supporting universal reference input port.
The Si5348 architecture also strengthens fourth generation DSPLL technology to provide jitter performance in a timing solution fully compliant with IEEE 1588, SyncE and Stratum 3 clocking requirements. The clock is designed to flawlessly integrate with IEEE 1588 software running on an external host processor. On a whole, it delivers a service that is 50 percent smaller in size, uses 35 percent lower power and 80 percent lower jitter than conventional synchronizers.
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