Cadence Offers Innovus Implementation System for Digital Signal Processor Design Projects

By CIOReview | Wednesday, January 20, 2016
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SAN JOSE, CA: Cadence Design Systems, a provider of Electronic design automation (EDA) and semiconductor IP, announces HiSilicons’ successful evaluation of the Cadence Innovus Implementation System that led to the adoption of the solution for 28nm and advanced node FinFET digital signal processor (DSP) design projects.

The Innovus Implementation System is a physical Implementation tool that enables HiSilicon to achieve a typical production power and performance of 1.2GHz while creating a 20 percent smaller design when compared with its previous solution. The implementation system features a variety of key capabilities which include: a parallel architecture to handle large designs and take advantage of multi-threading on multi-core workstations, optimized for industry-leading embedded processors, timing-and meet PPA (power, performance, and area) and TAT (turnaround time) requirements.

The system leverages GigaPlace solver-based placement technology, GigaOpt low-power optimization and CCOpt (Clock Concurrent Optimization) engines. GigaPlace solver-based placement technology is a slack-driven placement technique that is tightly integrated with Cadence’s timing- and power-driven optimization engine to enhance PPA. Clock Concurrent Optimization engine with true multithreading, merges physical optimization with clock-tree synthesis (CTS), simultaneously building clocks and optimizing logic delays based directly on a propagated clocks model.

The Innovus Implementation System helps engineers to provide technical assistance through phone, email or internet thereby delivering high-quality designs with best-in-class PPA with reduced development cost.

“The Innovus Implementation System was designed to address the capacity and PPA challenges of large complex designs, and we've seen HiSilicon improve both PPA and turnaround time simultaneously,” says Dr. Anirudh Devgan, senior vice president and general manager of the Digital and Signoff Group at Cadence.